1. Field of the Invention
This invention relates to semiconductor fabrication technologies, and more particularly, to a method of forming buried diffusion junctions (serving as source/drain regions) in conjunction with shallow-trench isolation (STI) structures in a semiconductor device. This method features the ability of buried diffusion junctions to be self-aligned and to serve as a plurality of parallel-spaced paired buried diffusion junctions with the STI structures formed therebetween and one of each pair of source/drain regions serving as a bit line.
2. Description of Related Art
MOS transistors (metal-oxide semiconductor transistor) are widely used as the basic switching elements in integrated circuits. A MOS transistor is typically composed of a gate, a source, and a drain. A semiconductor device usually consists of millions of MOS transistors; therefore isolation structures should be formed to electrically isolate the MOS transistors from each other. The isolation structures should be highly reliable in order to prevent possible short-circuits between the MOS transistors. A conventional method for forming isolation structures for MOS transistors is the so-called local oxidation of silicon (LOCOS) technique, which can be used to form thick field oxide layers on the substrate for isolating MOS transistors from each other. The LOCOS technique is able to provide highly reliable and effective isolation structures in the semiconductor device. However, it still has some drawbacks, such as stress and bird's beak problems. The bird's beak problem is particularly undesirable since it can cause the isolation structures to be less effective when the device is down sized for high integration. One solution to this problem is to use the so-called shallow-trench isolation (STI) structure in place of the LOCOS structure. The STI structure is not only effective in high-density devices, but is also highly solid and planarized.
In a semiconductor device with MOS transistors, bit lines are connected via contact holes to either the drain or the source of the MOS transistors so that data can be read out via the bit lines from the MOS transistors. In high-density devices, however, since the feature size is extremely small, the process for forming the contact holes is particularly difficult since it would be difficult to achieve precise alignment of the contact holes to the source/drain regions in the substrate. One solution to this problem is the so-called buried bit-line technique, which allows the bit lines to be formed in a buried manner that occupies only a small space in the substrate. One drawback to the buried bit-line structure, however, is that it does not allow the buried diffusion junctions and the STI structures to be formed on the same layout, due to the reason that the buried diffusion junctions will be broken up during the forming of the trenches used to form the STI structures. Moreover, by the conventional buried bit-line technique, the bit lines are formed after the bulk of the MOS transistors is finished, which would considerably increase the complexity of the fabrication process.